struct di_edid ¶

struct di_edid;

EDID data structure.

struct di_edid_chromaticity_coords ¶

struct di_edid_chromaticity_coords {
	float red_x, red_y;
	float green_x, green_y;
	float blue_x, blue_y;
	float white_x, white_y;
};

EDID display chromaticity coordinates, defined in section 3.7.

The values are accurate to the thousandth place. The red, green and blue values are zero for monochrome displays.

struct di_edid_color_encoding_formats ¶

struct di_edid_color_encoding_formats {
	bool rgb444; /* RGB 4:4:4 */
	bool ycrcb444; /* YCrCb 4:4:4 */
	bool ycrcb422; /* YCrCb 4:2:2 */
};

Basic color encoding formats, defined in section 3.6.4.

struct di_edid_color_management_data ¶

struct di_edid_color_management_data {
	int version;
	/* red polynomial coefficient a3 */
	float red_a3;
	/* red polynomial coefficient a2 */
	float red_a2;
	/* green polynomial coefficient a3 */
	float green_a3;
	/* green polynomial coefficient a2 */
	float green_a2;
	/* blue polynomial coefficient a3 */
	float blue_a3;
	/* blue polynomial coefficient a2 */
	float blue_a2;
};

EDID display Color Management Data, defined in section 3.10.3.7

Contains the coefficients for the function `L = a₃ × v³ + a₂ × v²` describing the luminance response L to some voltage v [0, 0.7] for each color channel.

For more information see VESA DCM Standard, Version 1; January 6, 2003

struct di_edid_color_point ¶

struct di_edid_color_point {
	/* White point index number */
	int index;
	/* The white chromaticity values, accurate to the thousandth place */
	float white_x, white_y;
	/* Gamma, zero if unset (ie, stored in an extension block) */
	float gamma;
};

EDID Color Points, defined in section 3.10.3.5.

struct di_edid_cvt_timing_code ¶

struct di_edid_cvt_timing_code {
	int32_t addressable_lines_per_field;
	enum di_edid_cvt_timing_code_aspect_ratio aspect_ratio;
	bool supports_50hz_sb;
	bool supports_60hz_sb;
	bool supports_75hz_sb;
	bool supports_85hz_sb;
	bool supports_60hz_rb;
	enum di_edid_cvt_timing_code_preferred_vrate preferred_vertical_rate;
};

EDID CVT Timing Code, defined in section 3.10.3.8

For more information see VESA Coordinated Video Timings (CVT) Standard.

struct di_edid_detailed_timing_analog_composite ¶

struct di_edid_detailed_timing_analog_composite {
	/* Sync with serrations (H-sync during V-sync) */
	 bool sync_serrations;
	/* Sync on green signal only (as opposed to all three
	 * RGB video signals) */
	 bool sync_on_green;
};

Flags for ANALOG_COMPOSITE signals

struct di_edid_detailed_timing_bipolar_analog_composite ¶

struct di_edid_detailed_timing_bipolar_analog_composite {
	/* Sync with serrations (H-sync during V-sync) */
	 bool sync_serrations;
	/* Sync on green signal only (as opposed to all three
	 * RGB video signals) */
	 bool sync_on_green;
};

Flags for BIPOLAR_ANALOG_COMPOSITE signals

struct di_edid_detailed_timing_def ¶

struct di_edid_detailed_timing_def {
	/* Pixel clock */
	int32_t pixel_clock_hz;
	/* Horizontal/Vertical Addressable Video in pixels/lines */
	int32_t horiz_video, vert_video;
	/* Horizontal/Vertical Blanking in pixels/lines */
	int32_t horiz_blank, vert_blank;
	/* Horizontal/Vertical Front Porch in pixels/lines */
	int32_t horiz_front_porch, vert_front_porch;
	/* Horizontal/Vertical Sync Pulse Width in pixels/lines */
	int32_t horiz_sync_pulse, vert_sync_pulse;
	/* Horizontal/Vertical Addressable Video Image Size in mm, zero if unset */
	int32_t horiz_image_mm, vert_image_mm;
	/* Horizontal/Vertical Border in pixels/lines */
	int32_t horiz_border, vert_border;
	/* Interlaced signal */
	 bool interlaced;
	/* Stereo Viewing Support */
	enum di_edid_detailed_timing_def_stereo stereo;
	/* Signal type */
	enum di_edid_detailed_timing_def_signal_type signal_type;
	/* Flags for ANALOG_COMPOSITE signals, NULL otherwise */
	const struct di_edid_detailed_timing_analog_composite *analog_composite;
	/* Flags for BIPOLAR_ANALOG_COMPOSITE signals, NULL otherwise */
	const struct di_edid_detailed_timing_bipolar_analog_composite *bipolar_analog_composite;
	/* Flags for DIGITAL_COMPOSITE signals, NULL otherwise */
	const struct di_edid_detailed_timing_digital_composite *digital_composite;
	/* Flags for DIGITAL_SEPARATE signals, NULL otherwise */
	const struct di_edid_detailed_timing_digital_separate *digital_separate;
};

EDID detailed timing definition, defined in section 3.10.2.

struct di_edid_detailed_timing_digital_composite ¶

struct di_edid_detailed_timing_digital_composite {
	/* Sync with serrations (H-sync during V-sync) */
	 bool sync_serrations;
	/* Horizontal polarity (outside of V-sync) */
	enum di_edid_detailed_timing_def_sync_polarity sync_horiz_polarity;
};

Flags for DIGITAL_COMPOSITE signals

struct di_edid_detailed_timing_digital_separate ¶

struct di_edid_detailed_timing_digital_separate {
	/* Vertical polarity */
	enum di_edid_detailed_timing_def_sync_polarity sync_vert_polarity;
	/* Horizontal polarity (outside of V-sync) */
	enum di_edid_detailed_timing_def_sync_polarity sync_horiz_polarity;
};

Flags for DIGITAL_SEPARATE signals

struct di_edid_display_descriptor ¶

struct di_edid_display_descriptor;

EDID display descriptor.

struct di_edid_display_range_limits ¶

struct di_edid_display_range_limits {
	/* Vertical rate limits in Hz, from 1 Hz to 510 Hz */
	int32_t min_vert_rate_hz, max_vert_rate_hz;
	/* Horizontal rate limits in Hz, from 1 KHz to 510 KHz, rounded to the
	 * nearest multiple of 1 KHz */
	int32_t min_horiz_rate_hz, max_horiz_rate_hz;
	
	/* Maximum pixel clock in Hz, zero if unset, rounded to the nearest
	 * multiple of 0.25 MHz if CVT, otherwise to the nearest multiple of
	 * 10 MHz */
	int64_t max_pixel_clock_hz;
	
	enum di_edid_display_range_limits_type type;
	
	/* For SECONDARY_GTF limits, NULL otherwise */
	const struct di_edid_display_range_limits_secondary_gtf *secondary_gtf;
	/* For CVT limits, NULL otherwise */
	const struct di_edid_display_range_limits_cvt *cvt;
};

EDID display range limits, defined in section 3.10.3.3.1.

struct di_edid_display_range_limits_cvt ¶

struct di_edid_display_range_limits_cvt {
	int32_t version, revision;
	/* Maximum active pixels per line, zero for no limit */
	int32_t max_horiz_px;
	/* Supported aspect ratio, bitfield of enum di_edid_cvt_aspect_ratio */
	uint32_t supported_aspect_ratio;
	/* Preferred aspect ratio */
	enum di_edid_cvt_aspect_ratio preferred_aspect_ratio;
	/* Whether standard CVT blanking is supported */
	 bool standard_blanking;
	/* Whether reduced CVT blanking is supported */
	 bool reduced_blanking;
	/* Supported types of display scaling, bitfield of
	 * enum di_edid_cvt_scaling */
	uint32_t supported_scaling;
	/* Preferred vertical refresh rate, in Hz */
	int32_t preferred_vert_refresh_hz;
};

struct di_edid_display_range_limits_secondary_gtf ¶

struct di_edid_display_range_limits_secondary_gtf {
	/* Start break frequency in Hz */
	int start_freq_hz;
	/* C, M, K, J parameters */
	float c, m, k, j;
};

struct di_edid_dpms ¶

struct di_edid_dpms {
	bool standby;
	bool suspend;
	bool off;
};

Supported legacy Display Power Management Signaling (DPMS) states, defined in section 3.6.4.

Display Power Management (DPM) compliant displays only support "off".

struct di_edid_established_timings_i_ii ¶

struct di_edid_established_timings_i_ii {
	/* Established timings I */
	 bool has_720x400_70hz; /* 720 x 400 @ 70Hz (IBM, VGA) */
	bool has_720x400_88hz; /* 720 x 400 @ 88Hz (IBM, XGA2) */
	bool has_640x480_60hz; /* 640 x 480 @ 60Hz (IBM, VGA) */
	bool has_640x480_67hz; /* 640 x 480 @ 67Hz (Apple, Mac II) */
	bool has_640x480_72hz; /* 640 x 480 @ 72Hz (VESA) */
	bool has_640x480_75hz; /* 640 x 480 @ 75Hz (VESA) */
	bool has_800x600_56hz; /* 800 x 600 @ 56Hz (VESA) */
	bool has_800x600_60hz; /* 800 x 600 @ 60Hz (VESA) */
	
	/* Established timings II */
	 bool has_800x600_72hz; /* 800 x 600 @ 72Hz (VESA) */
	bool has_800x600_75hz; /* 800 x 600 @ 75Hz (VESA) */
	bool has_832x624_75hz; /* 832 x 624 @ 75Hz (Apple, Mac II) */
	bool has_1024x768_87hz_interlaced; /* 1024 x 768 @ 87Hz interlaced (IBM) */
	bool has_1024x768_60hz; /* 1024 x 768 @ 60Hz (VESA) */
	bool has_1024x768_70hz; /* 1024 x 768 @ 70Hz (VESA) */
	bool has_1024x768_75hz; /* 1024 x 768 @ 75Hz (VESA) */
	bool has_1280x1024_75hz; /* 1280 x 1024 @ 75Hz (VESA) */
	
	bool has_1152x870_75hz; /* 1152 x 870 @ 75Hz (Apple, Mac II) */
};

Established timings I and II, defined in section 3.8.

struct di_edid_ext ¶

struct di_edid_ext;

EDID extension block.

struct di_edid_misc_features ¶

struct di_edid_misc_features {
	/**
	 * First detailed timing is the preferred timing.
	 *
	 * Always set for EDID 1.4 and later.
	 */
	 bool has_preferred_timing;
	/**
	 * GTF using the default parameters is supported.
	 *
	 * Never set for EDID 1.4 and later.
	 */
	 bool default_gtf;
	/**
	 * sRGB standard default color space is primary color space.
	 */
	 bool srgb_is_primary;
	/**
	 * Preferred timing mode includes native pixel format and rate.
	 *
	 * Never set for EDID 1.3 and earlier.
	 */
	 bool preferred_timing_is_native;
	/**
	 * GTF or CVT generated timings within the display's range limits are
	 * accepted.
	 *
	 * Never set for EDID 1.3 and earlier.
	 */
	 bool continuous_freq;
};

Miscellaneous basic features, defined in section 3.6.4.

Note, the enum values don't match the specification.

struct di_edid_screen_size ¶

struct di_edid_screen_size {
	/* Physical size in centimeters, zero if unset */
	int width_cm, height_cm;
	/* Aspect ratio rounded to the hundredth decimal place, zero if unset. */
	float landscape_aspect_ratio, portait_aspect_ratio;
};

struct di_edid_standard_timing ¶

struct di_edid_standard_timing {
	/* Horizontal addressable pixels */
	int32_t horiz_video;
	/* Aspect ratio */
	enum di_edid_standard_timing_aspect_ratio aspect_ratio;
	/* Field Refresh Rate in Hz */
	int32_t refresh_rate_hz;
};

EDID standard timing, defined in section 3.9.

struct di_edid_vendor_product ¶

struct di_edid_vendor_product {
	char manufacturer[];
	uint16_t product;
	uint32_t serial; /* zero if unset */
	
	/* These fields are zero if unset */
	int manufacture_week;
	int manufacture_year;
	int model_year;
};

EDID vendor & product identification.

struct di_edid_video_input_analog ¶

struct di_edid_video_input_analog {
	enum di_edid_video_input_analog_signal_level_std signal_level_std;
	enum di_edid_video_input_analog_video_setup video_setup;
	
	/* Separate Sync H & V Signals are supported */
	 bool sync_separate;
	/* Composite Sync Signal on Horizontal is supported */
	 bool sync_composite;
	/* Composite Sync Signal on Green Video is supported */
	 bool sync_on_green;
	/* Serration on the Vertical Sync is supported */
	 bool sync_serrations;
};

EDID analog video input basic information, defined in section 3.6.1.

struct di_edid_video_input_digital ¶

struct di_edid_video_input_digital {
	/* EDID 1.2 and 1.3 */
	 bool dfp1; /* Compatible with VESA DFP 1.x TDMS CRGB */
	
	/* EDID 1.4 and later */
	int color_bit_depth; /* zero if undefined */
	enum di_edid_video_input_digital_interface interface;
};

EDID digital video input basic information, defined in section 3.6.1.